regarding the change of names mentioned in the document, such as mitsubishi electric and mitsubishi xx, to renesas technology corp. the semiconductor operations of hitachi and mitsubishi electric were transferred to renesas technology corporation on april 1st 2003. these operations include microcomputer, logic, analog and discrete devices, and memory chips other than drams (flash memory, srams etc.) accordingly, although mitsubishi electric, mitsubishi electric corporation, mitsubishi semiconductors, and other mitsubishi brand names are mentioned in the document, these names have in fact all been changed to renesas technology corp. thank you for your understanding. except for our corporate trademark, logo and corporate statement, no changes whatsoever have been made to the contents of the document, and these changes do not constitute any alteration to the contents of the document itself. note : mitsubishi electric will continue the business operations of high frequency & optical devices and power devices. renesas technology corp. customer support dept. april 1, 2003 to all our customers
mitsubishi 8-bit single-chip microcomputer 740 family / 38000 series 3886 group user s manual
keep safety first in your circuit designs! notes regarding these materials mitsubishi electric corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. trouble with semiconductors may lead to personal injury, fire or property damage. remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. these materials are intended as a reference to assist our customers in the selection of the mitsubishi semiconductor product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to mitsubishi electric corporation or a third party. mitsubishi electric corporation assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by mitsubishi electric corporation without notice due to product improvements or other reasons. it is therefore recommended that customers contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. mitsubishi electric corporation assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by mitsubishi electric corporation by various means, including the mitsubishi semiconductor home page (http:// www.mitsubishichips.com). when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. mitsubishi electric corporation assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. mitsubishi electric corporation semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. the prior written approval of mitsubishi electric corporation is necessary to reprint or reproduce in whole or in part these materials. if these products or technologies are subject to the japanese export control restrictions, they must be exported under a license from the japanese government and cannot be imported into a country other than the approved destination. any diversion or reexport contrary to the export control laws and regulations of japan and/ or the country of destination is prohibited. please contact mitsubishi electric corporation or an authorized mitsubishi semiconductor product distributor for further details on these materials or the products contained therein.
rev. rev. no. date 1.0 first edition 990215 2.0 explanations of 1. organization of before using this manual are partly revised. 000922 page 1-2; explanations of power dissipation of features are partly eliminated. page 1-2; explanations of memory expansion possible of features are partly revised. page 1-2; value of program/erase voltage of is revised. page 1-2; operating temperature range of is added. page 1-2; explanations of notes are partly revised. page 1-2; explanations of application are partly added. page 1-3; product name and note into figure 1 are partly added. page 1-3; note into figure 2 is added. page 1-4; figure 3 is added. page 1-5; figure 4 is partly revised. page 1-8; figure 5 is partly revised. page 1-9; explanations of packages are partly added. page 1-9; figure 6 is partly revised. page 1-9; table 3 is partly added. page 1-13; figure 9 is partly revised. page 1-14; notes into figure 10 are partly revised. page 1-16; related sfrs of p4 2 /int 0 /obf 00 , p4 3 /int 1 /obf 01 into table 6 are partly added. page 1-42; [port control register 2 (pctl2)] are added. page 1-46; explanations of bit 5 of [i 2 c clock control register (s2)] are partly revised. page 1-48; bit name of bit 4 of [i 2 c status register (s1)] is revised. page 1-49; bit name of bit 4 into figure 41 is revised. page 1-54; explanations of (3) restart condition generating procedure are partly revised. page 1-54; (6) stop condition input at 7th clock pulse is added. page 1-54; (7) es0 bit switch is added. page 1-55; figure 50 is partly revised. revision description list 3886 group user s manual (1/6) revision description
rev. rev. no. date 2.0 page 1-55; figure 50 is partly revised. 000922 page 1-60; explanations of reset circuit are partly revised. page 1-60; explanations of note into figure 57 are added. page 1-63; note 2 into figure 62 is added. page 1-64; figure 63 is partly revised. page 1-65; explanations of processor mode are partly revised. page 1-65; explanations of (2) memory expansion mode are partly added. page 1-65; explanations of (3) microprocessor mode are partly revised. page 1-65; explanations into figure 64 are partly eliminated. page 1-65; note into figure 65 is partly revised. page 1-66; explanations of bus control at memory expansion are partly revised. page 1-69; explanations of cnvss into table 22 are partly revised. page 1-70; figure 68 is partly revised. page 1-78; figure 74 is partly revised. page 1-79; explanations of cnvss into table 27 are partly revised. page 1-83; note is added. page 1-85; explanations of functional outline of (3) flash memory mode 3 (cpu reprogram -ming mode) are partly added. page 1-85; note into figure 81 is partly eliminated. page 1-86; explanations of of cpu reprogramming mode operation procedure are partly eliminated. page 1-86; figure 83 is partly revised. page 1-89; explanations of a-d converter of notes on programming are partly eliminated. page 1-90; explanations of handling of power source pins of notes on usage are partly revised. page 1-90; erasing of flash memory version is added. revision description list 3886 group user s manual (2/6) revision description
rev. rev. no. date 2.0 page 1-90; explanations of data required for one time prom programming 000922 orders are partly added. page 1-91; interrupt of functional description supplement is eliminated. page 1-91; timing after interrupt of functional description supplement is eliminated. 2.2 interrupt is added. 2.8 d-a converter is added. 2.12 clock generating circuit is added. 2.13 standby function is added. 2.15 flash memory is added. page 2-4; bit attributes into figure 2.1.4 are partly revised. page 2-4; bit attributes into figure 2.1.5 are partly revised. page 2-5; explanations of 2.1.3 port p4/p7 input register are partly added. page 2-6; explanations of reason of (1) notes in stand-by state are partly revised. page 2-7; explanations of ? input ports and i/o ports of (1) terminate unused pins are partly revised. page 2-24; figure 2.3.1 is partly revised. page 2-27; figure 2.3.6 is added. page 2-31; figure 2.3.12 is partly revised. page 2-32; figure 2.3.13 is partly revised. page 2-41; explanations of 2.3.4 notes on timer are partly revised. page 2-75; explanations of (7) transmit interrupt request when transmit enable bit is set are partly revised. page 2-75; (8) transmit data writing is added. page 2-87; clause name and explanations of 2.5.6 i 2 c-bus communication usage example are partly revised. page 2-88; figure 2.5.17 is partly revised. page 2-104; explanations of (2) procedure for generating start condition are partly added. revision description list 3886 group user s manual (3/6) revision description
rev. rev. no. date 2.0 page 2-104; sub clause name and explanations of (3) procedure for generating restart 000922 condition are partly revised. page 2-105; explanations of (6) stop condition input at 7th clock pulse are partly revised. page 2-105; clause of notes on programming for smbus interface in rev.1.0 is eliminated. page 2-118; explanations of note into figure 2.7.9 are partly revised. page 2-120; explanations of (2) a-d converter power source pin of 2.7.4 notes on a-d converter are partly eliminated. page 2-120; explanations of (3) clock frequency during a-d conversion are partly eliminated. page 2-128; figure 2.9.1 is partly revised. page 2-129; figure 2.9.3 is partly revised. page 2-132; figure 2.9.8 is added. page 2-138; figure 2.10.3 is partly revised. page 2-139; figure 2.10.4 is partly revised. page 2-141; figure 2.11.2 is partly revised. page 2-150; explanations of (3) notes on using stop mode are partly revised. page 2-154; figure 2.14.2 is partly revised. page 2-156; figure 2.14.4 is partly revised. page 2-156; figure 2.14.5 is partly revised. page 2-157; figure 2.14.6 is partly revised. page 2-160; figure 2.14.9 is partly revised. page 2-160; figure 2.14.10 is partly revised. page 2-161; figure 2.14.11 is partly revised. page 2-165; table 2.15.2 is partly revised. paragraph of mask rom confirmation in rev.1.0 is eliminated. paragraph of rom programming confirmation form in rev.1.0 is eliminated. paragraph of mark specification form in rev.1.0 is eliminated. revision description list 3886 group user s manual (4/6) revision description
rev. rev. no. date 2.0 for the mask rom confirmation form, the rom programming confirmation form, and the 000922 mark specifications, refer to the mitsubishi mcu technical information homepage. *data required for rom orders (mask rom confirmation forms, rom programming confirmation forms) http://www.infomicom.mesc.co.jp/38000/38ordere.htm *mark specification forms http://www.infomicom.mesc.co.jp/mela/markform.htm page 3-8; limit of tw(reset) into table 3.1.11 is revised. page 3-9; limit of tw(reset) into table 3.1.12 is revised. page 3-18; figure 3.2.1 is partly revised. page 3-18; figure 3.2.2 is revised. page 3-19; figure 3.2.3 is revised. page 3-19; figure 3.2.4 is revised. page 3-20; figure 3.2.5 is revised. page 3-20; figure 3.2.6 is revised. page 3-21; figure 3.2.7 is revised. page 3-24; figure 3.2.12 is partly revised. page 3-28; explanations of reason of (1) notes in stand-by state of 3.3.1 notes on input and output pins are partly added. page 3-29; explanations of ? input ports of (1) terminate unused pins of 3.3.2 termination of unused pins is partly revised. page 3-29; explanations of i/o ports of (1) terminate unused pins of 3.3.2 termination of unused pins is partly revised. page 3-30; sub clause of setting of interrupt request bit and interrupt enable bit in rev. 1.0 is eliminated. page 3-31; (3) change of relevant register setting of 3.3.3 notes on interrupts is added. page 3-34; explanations of (5) data transmission control with referring to transmit shift register completion flag are partly added. revision description list 3886 group user s manual (5/6) revision description
rev. rev. no. date 2.0 page 3-34; explanations of (7) transmit interrupt request when transmit enable bit is set are 000922 partly revised. page 3-35; explanations of (2) procedure for generating start condition using multi-master are partly added. page 3-36; explanations of (3) procedure for generating restart condition are partly added. page 3-36; sub clause of stop condition generating procedure in master is eliminated. page 3-36; explanations of (6) stop condition input at 7th clock pulse are partly added. page 3-37; explanations of (2) a-d converter power source pin are partly revised. page 3-37; explanations of (3) clock frequency during a-d conversion are partly revised. page 3-37; 3.3.9 notes on d-a converter is added. page 3-38; 3.3.12 notes on cpu reprogramming mode is added. page 3-38; 3.3.13 notes on using stop mode is added. page 3-39; 3.3.14 notes on wait mode is added. page 3-39; explanations of 3.3.16 notes on restarting oscillation are partly revised. page 3-41; figure 3.3.10 is partly revised. page 3-50; figure 3.5.1 is partly revised. page 3-50; figure 3.5.2 is partly revised. page 3-62; bit attributes into figure 3.5.22 are partly revised. page 3-64; bit attributes into figure 3.5.25 are partly revised. page 3-64; bit attributes into figure 3.5.26 are partly revised. page 3-70; figure 3.5.37 is partly revised. page 3-73; figure 3.5.42 is added. page 3-74; figure 3.5.43 is added. page 3-87; product name and note into figure 3.10.1 are partly added. page 3-87; note into figure 3.10.2 is added. page 3-88; figure 3.10.3 is added. revision description list 3886 group user s manual (6/6) revision description
preface this user s manual describes mitsubishi s cmos 8- bit microcomputers 3886 group. after reading this manual, the user should have a through knowledge of the functions and features of the 3886 group, and should be able to fully utilize the product. the manual starts with specifications and ends with application examples. for details of software, refer to the 740 family software manual. for details of development support tools, refer to the mitsubishi microcomputer development support tools homepage (http://www.tool-spt.mesc.co.jp/index_e.htm).
before using this manual this user s manual consists of the following three chapters. refer to the chapter appropriate to your conditions, such as hardware design or software development. chapter 3 also includes necessary information for systems development. you must refer to that chapter. 1. organization chapter 1 hardware this chapter describes features of the microcomputer and operation of each peripheral function. chapter 2 application this chapter describes usage and application examples of peripheral functions, based mainly on setting examples of relevant registers. chapter 3 appendix this chapter includes necessary information for systems development using the microcomputer, such as the electrical characteristics, the notes, and the list of registers. ? for the mask rom confirmation form, the rom programming confirmation form, and the mark specifications, refer to the mitsubishi mcu technical information homepage (http:// www.infomicom.mesc.co.jp/). 2. structure of register the figure of each register structure describes its functions, contents at reset, and attributes as follows : n o t e 2 : b i t a t t r i b u t e s . . . . . . . . .t h e a t t r i b u t e s o f c o n t r o l r e g i s t e r b i t s a r e c l a s s i f i e d i n t o 3 b y t e s : r e a d - o n l y , w r i t e - o n l y a n d r e a d a n d w r i t e . i n t h e f i g u r e , t h e s e a t t r i b u t e s a r e r e p r e s e n t e d a s f o l l o w s : : b i t i n w h i c h n o t h i n g i s a r r a n g e d 0 1 : n a m e function a t reset rw b 0 1 2 3 4 0 0 0 0 0 ? ? 5 6 7 1 b 0 b 1 b 2 b 3 b 4 b 5 b 6 b 7 contents immediately after reset release bit attributes (n ote 1 ) p r o c e s s o r m o d e b i t s s t a c k p a g e s e l e c t i o n b i t n o t h i n g a r r a n g e d f o r t h e s e b i t s . t h e s e a r e w r i t e d i s a b l e d b i t s . w h e n t h e s e b i t s a r e r e a d o u t , t h e c o n t e n t s a r e 0 . fix this bit to 0. m a i n c l o c k ( x i n - x o u t ) s t o p b i t internal system clock selection bit 0 0 : si ng l e-c hi p mo d e 1 0 : 1 1 : n ot ava il a bl e b1 b0 0 : 0 page 1 : 1 page 0 : o perat i ng 1 : s toppe d 0 : x in - x out se l ecte d 1 : x cin - x cout se l ecte d : b i t t h a t i s n o t u s e d f o r c o n t r o l o f t h e c o r r e s p o n d i n g f u n c t i o n 0 n o t e 1 : . c o n t e n t s i m m e d i a t e l y a f t e r r e s e t r e l e a s e 0 . . . . . . . 0 a t r e s e t r e l e a s e 1 . . . . . . . 1 a t r e s e t r e l e a s e ? . . . . . . .u n d e f i n e d a t r e s e t r e l e a s e ? . . . . . . .c o n t e n t s d e t e r m i n e d b y o p t i o n a t r e s e t r e l e a s e r....... read ...... read enabled ? .......read disabled w......write ..... write enabled ? ...... write disabled (n ote 2 ) cpu mode register (cpum) [address : 3b 16 ] bits ? ?
i 3886 group user s manual table of contents table of contents chapter 1 hardware description ............................................................................................................................... . 1-2 features ............................................................................................................................... ..... 1-2 application ............................................................................................................................... . 1-2 pin configuration .................................................................................................................. 1-3 functional block .................................................................................................................. 1-5 pin description ........................................................................................................................ 1-6 part numbering ....................................................................................................................... 1-8 group expansion .................................................................................................................... 1-9 memory type ............................................................................................................................ 1-9 memory size ............................................................................................................................. 1- 9 packages ............................................................................................................................... .... 1-9 functional description .................................................................................................... 1-10 central processing unit (cpu) ............................................................................................ 1-10 memory ............................................................................................................................... ..... 1-14 i/o ports ............................................................................................................................... ... 1-16 interrupts ..................................................................................................................... ............ 1-23 key input interrupt (key-on wake up) ................................................................................ 1-27 timers ............................................................................................................................... ....... 1-28 serial i/o ............................................................................................................................... .. 1-30 pulse width modulation (pwm) output circuit .................................................................. 1-36 bus interface ........................................................................................................................... 1-39 multi-master i 2 c-bus interface ............................................................................................. 1-44 a-d converter ......................................................................................................................... 1-55 d-a converter ......................................................................................................................... 1-57 comparator circuit ................................................................................................................. 1-58 watchdog timer ..................................................................................................................... 1-59 reset circuit ........................................................................................................................... 1-60 clock generating circuit ....................................................................................................... 1-62 processor mode ...................................................................................................................... 1-65 bus control at memory expansion ...................................................................................... 1-66 eprom mode ......................................................................................................................... 1-67 flash memory mode .............................................................................................................. 1-68 notes on programming ..................................................................................................... 1-89 notes on usage ..................................................................................................................... 1-90 data required for mask orders ................................................................................ 1-90 data required for one time prom programming orders ............................. 1-90 functional description supplement ......................................................................... 1-91 chapter 2 application 2.1 i/o port ............................................................................................................................... ...... 2-2 2.1.1 memory map ................................................................................................................... 2-2 2.1.2 relevant registers .......................................................................................................... 2-3 2.1.3 port p4/p7 input register .............................................................................................. 2-5 2.1.4 handling of unused pins ............................................................................................... 2-5 2.1.5 notes on input and output pins ................................................................................... 2-6 2.1.6 termination of unused pins .......................................................................................... 2-7
ii 3886 group user s manual table of contents 2.2 interrupt ............................................................................................................................... .... 2-8 2.2.1 memory map ................................................................................................................... 2-8 2.2.2 relevant registers .......................................................................................................... 2-8 2.2.3 interrupt source ............................................................................................................ 2-12 2.2.4 interrupt operation ........................................................................................................ 2-13 2.2.5 interrupt control ............................................................................................................ 2-16 2.2.6 int interrupt .................................................................................................................. 2-19 2.2.7 key input interrupt ....................................................................................................... 2-20 2.2.8 notes on interrupts ...................................................................................................... 2-22 2.3 timer ............................................................................................................................... ........ 2-24 2.3.1 memory map ................................................................................................................. 2-24 2.3.2 relevant registers ........................................................................................................ 2-24 2.3.3 timer application examples ........................................................................................ 2-30 2.3.4 notes on timer .............................................................................................................. 2-41 2.4 serial i/o ............................................................................................................................... . 2-42 2.4.1 memory map ................................................................................................................. 2-42 2.4.2 relevant registers ........................................................................................................ 2-43 2.4.3 serial i/o connection examples ................................................................................. 2-50 2.4.4 setting of serial i/o transfer data format ................................................................. 2-52 2.4.5 serial i/o application examples ................................................................................. 2-53 2.4.6 notes on serial i/o ...................................................................................................... 2-73 2.5 multi-master i 2 c-bus interface ......................................................................................... 2-76 2.5.1 memory map ................................................................................................................. 2-76 2.5.2 relevant registers ........................................................................................................ 2-76 2.5.3 i 2 c-bus overview ......................................................................................................... 2-83 2.5.4 communication format ................................................................................................. 2-84 2.5.5 synchronization and arbitration lost .......................................................................... 2-85 2.5.6 i 2 c-bus communication usage example ................................................................... 2-87 2.5.7 notes on multi-master i 2 c-bus interface ............................................................... 2-103 2.6 pwm ............................................................................................................................... ....... 2-106 2.6.1 memory map ............................................................................................................... 2-106 2.6.2 relevant registers ...................................................................................................... 2-107 2.6.3 pwm application example ......................................................................................... 2-111 2.6.4 notes on pwm ........................................................................................................... 2-113 2.7 a-d converter ..................................................................................................................... 2-114 2.7.1 memory map ............................................................................................................... 2-114 2.7.2 relevant registers ...................................................................................................... 2-114 2.7.3 a-d converter application examples ........................................................................ 2-118 2.7.4 notes on a-d converter ............................................................................................ 2-120 2.8 d-a converter ..................................................................................................................... 2-121 2.8.1 memory map ............................................................................................................... 2-121 2.8.2 relevant registers ...................................................................................................... 2-122 2.8.3 d-a converter application example .......................................................................... 2-124 2.8.4 notes on d-a converter ............................................................................................ 2-127 2.9 bus interface ...................................................................................................................... 2-128 2.9.1 memory map ............................................................................................................... 2-128 2.9.2 relevant registers ...................................................................................................... 2-129 2.9.3 bus interface overview .............................................................................................. 2-133 2.9.4 input/output operation ............................................................................................... 2-134 2.9.5 relevant registers setting ......................................................................................... 2-135 2.10 watchdog timer ................................................................................................................ 2-137 2.10.1 memory map ............................................................................................................. 2-137
iii 3886 group user s manual table of contents 2.10.2 relevant registers .................................................................................................... 2-137 2.10.3 watchdog timer application examples ................................................................. 2-139 2.10.4 notes on watchdog timer ........................................................................................ 2-140 2.11 reset ............................................................................................................................... ...2-141 2.11.1 connection example of reset ic ............................................................................ 2-141 2.11.2 notes on reset pin ............................................................................................... 2-142 2.12 clock generating circuit ................................................................................................ 2-143 2.12.1 relevant registers .................................................................................................... 2-143 2.12.2 clock generating circuit application example ....................................................... 2-144 2.13 standby function ............................................................................................................. 2-147 2.13.1 stop mode ................................................................................................................. 2-147 2.13.2 wait mode ................................................................................................................. 2-151 2.14 processor mode ............................................................................................................... 2-154 2.14.1 memory map ............................................................................................................. 2-154 2.14.2 relevant registers .................................................................................................... 2-154 2.14.3 processor mode usage examples ........................................................................ 2-155 2.15 flash memory ................................................................................................................... 2-162 2.15.1 overview .................................................................................................................... 2-162 2.15.2 memory map ............................................................................................................. 2-162 2.15.3 relevant registers .................................................................................................... 2-163 2.15.4 parallel i/o mode ..................................................................................................... 2-164 2.15.5 serial i/o mode ........................................................................................................ 2-165 2.15.6 cpu reprogramming mode ..................................................................................... 2-166 2.15.7 flash memory mode application examples .......................................................... 2-167 2.15.8 notes on cpu reprogramming mode .................................................................... 2-176 chapter 3 appendix 3.1 electrical characteristics ..................................................................................................... 3-2 3.1.1 absolute maximum ratings ............................................................................................ 3-2 3.1.2 recommended operating conditions ............................................................................ 3-3 3.1.3 electrical characteristics ................................................................................................ 3-5 3.1.4 a-d converter characteristics ....................................................................................... 3-7 3.1.5 d-a converter characteristics ....................................................................................... 3-7 3.1.6 comparator characteristics ........................................................................................... 3-7 3.1.7 timing requirements ...................................................................................................... 3-8 3.1.8 timing requirements for system bus interface ......................................................... 3-10 3.1.9 switching characteristics ............................................................................................. 3-11 3.1.10 switching characteristics for system bus interface ............................................... 3-11 3.1.11 timing requirements in memory expansion mode and microprocessor mode .. 3-12 3.1.12 switching characteristics in memory expansion mode and microprocessor mode .. 3-12 3.1.13 multi-master i 2 c-bus bus line characteristics ....................................................... 3-17 3.2 standard characteristics .................................................................................................... 3-18 3.2.1 power source current characteristic examples ........................................................ 3-18 3.2.2 port standard characteristic examples ...................................................................... 3-22 3.2.3 input port standard characteristic examples ............................................................ 3-25 3.2.4 a-d conversion standard characteristics ................................................................... 3-26 3.2.5 d-a conversion standard characteristics ................................................................... 3-27 3.3 notes on use ........................................................................................................................ 3-28 3.3.1 notes on input and output pins ................................................................................. 3-28 3.3.2 termination of unused pins ........................................................................................ 3-29 3.3.3 notes on interrupts ...................................................................................................... 3-30 3.3.4 notes on timer .............................................................................................................. 3-31
iv 3886 group user s manual table of contents 3.3.5 notes on serial i/o ...................................................................................................... 3-32 3.3.6 notes on multi-master i 2 c-bus interface ................................................................. 3-35 3.3.7 notes on pwm ............................................................................................................. 3-37 3.3.8 notes on a-d converter .............................................................................................. 3-37 3.3.9 notes on d-a converter .............................................................................................. 3-37 3.3.10 notes on watchdog timer .......................................................................................... 3-38 3.3.11 notes on reset pin ................................................................................................. 3-38 3.3.12 notes on cpu reprogramming mode ...................................................................... 3-38 3.3.13 notes on using stop mode ....................................................................................... 3-38 3.3.14 notes on wait mode .................................................................................................. 3-39 3.3.15 notes on low-speed operation mode ...................................................................... 3-39 3.3.16 notes on restarting oscillation .................................................................................. 3-39 3.3.17 notes on programming .............................................................................................. 3-40 3.3.18 programming and test of built-in prom version ................................................... 3-42 3.3.19 notes on built-in prom version .............................................................................. 3-43 3.4 countermeasures against noise ...................................................................................... 3-44 3.4.1 shortest wiring length .................................................................................................. 3-44 3.4.2 connection of bypass capacitor across vss line and vcc line ............................. 3-46 3.4.3 wiring to analog input pins ........................................................................................ 3-46 3.4.4 oscillator concerns ....................................................................................................... 3-47 3.4.5 setup for i/o ports ....................................................................................................... 3-48 3.4.6 providing of watchdog timer function by software .................................................. 3-49 3.5 list of registers ................................................................................................................... 3-50 3.6 package outline ................................................................................................................... 3-75 3.7 machine instructions .......................................................................................................... 3-76 3.8 list of instruction code ..................................................................................................... 3-87 3.9 sfr memory map ................................................................................................................ 3-88 3.10 pin configurations ........................................................................................................ ..... 3-89
v 3886 group user s manual list of figures list of figures chapter 1 hardware fig. 1 m38867m8a-xxxhp, m38867e8ahp pin configuration ................................................ 1-3 fig. 2 m38867e8afs pin configuration ...................................................................................... 1-3 fig. 3 m38869mfa-xxxgp/hp, m38869ffagp/hp pin configuration ................................... 1-4 fig. 4 functional block diagram ................................................................................................... 1-5 fig. 5 part numbering .................................................................................................................... 1-8 fig. 6 memory expansion plan ..................................................................................................... 1-9 fig. 7 740 family cpu register structure ................................................................................. 1-10 fig. 8 register push and pop at interrupt generation and subroutine call ......................... 1-11 fig. 9 structure of cpu mode register ..................................................................................... 1-13 fig. 10 memory map diagram .................................................................................................... 1-14 fig. 11 memory map of special function register (sfr) ........................................................ 1-15 fig. 12 port block diagram (1) ................................................................................................... 1-18 fig. 13 port block diagram (2) ................................................................................................... 1-19 fig. 14 port block diagram (3) ................................................................................................... 1-20 fig. 15 port block diagram (4) ................................................................................................... 1-21 fig. 16 structure of port i/o related registers ......................................................................... 1-22 fig. 17 interrupt control ............................................................................................................... 1-25 fig. 18 structure of interrupt-related registers (1) .................................................................. 1-25 fig. 19 structure of interrupt-related registers (2) .................................................................. 1-26 fig. 20 connection example when using key input interrupt and port p3 block diagram... 1-27 fig. 21 structure of timer xy mode register ............................................................................ 1-28 fig. 22 block diagram of timer x, timer y, timer 1, and timer 2 ......................................... 1-29 fig. 23 block diagram of clock synchronous serial i/o1 ........................................................ 1-30 fig. 24 operation of clock synchronous serial i/o1 function ................................................ 1-30 fig. 25 block diagram of uart serial i/o1 ............................................................................. 1-31 fig. 26 operation of uart serial i/o1 function ...................................................................... 1-32 fig. 27 structure of serial i/o1 control registers ..................................................................... 1-33 fig. 28 structure of serial i/o2 control register ....................................................................... 1-34 fig. 29 block diagram of serial i/o2 function .......................................................................... 1-34 fig. 30 timing of serial i/o2 function ....................................................................................... 1-35 fig. 31 pwm block diagram (pwm0) ........................................................................................ 1-36 fig. 32 pwm timing ..................................................................................................................... 1-37 fig. 33 14-bit pwm timing (pwm0) .......................................................................................... 1-38 fig. 34 interrupt request circuit of data bus buffer ................................................................. 1-39 fig. 35 structure of bus interface related register .................................................................. 1-40 fig. 36 bus interface device block diagram ............................................................................. 1-41 fig. 37 block diagram of multi-master i 2 c-bus interface ...................................................... 1-44 fig. 38 structure of i 2 c address register .................................................................................. 1-45 fig. 39 structure of i 2 c clock control register ......................................................................... 1-46 fig. 40 structure of i 2 c control register .................................................................................... 1-47 fig. 41 structure of i 2 c status register ..................................................................................... 1-49 fig. 42 interrupt request signal generating timing .................................................................. 1-49 fig. 43 start condition generating timing diagram .............................................................. 1-50 fig. 44 stop condition generating timing diagram ................................................................ 1-50 fig. 45 start condition detecting timing diagram ................................................................. 1-50
vi 3886 group user s manual list of figures fig. 46 stop condition detecting timing diagram ................................................................... 1-50 fig. 47 structure of i 2 c start/stop condition control register ......................................... 1-52 fig. 48 address data communication format ............................................................................ 1-52 fig. 49 structure of ad/da control register ............................................................................. 1-55 fig. 50 structure of 10-bit a-d mode reading ......................................................................... 1-55 fig. 51 block diagram of a-d converter ................................................................................... 1-56 fig. 52 block diagram of d-a converter ................................................................................... 1-57 fig. 53 equivalent connection circuit of d-a converter (da1) ............................................... 1-57 fig. 54 comparator circuit .......................................................................................................... 1-58 fig. 55 block diagram of watchdog timer ................................................................................ 1-59 fig. 56 structure of watchdog timer control register ............................................................. 1-59 fig. 57 reset circuit example .................................................................................................... 1-60 fig. 58 reset sequence .............................................................................................................. 1-60 fig. 59 internal status at reset ............................................................................................... ... 1-61 fig. 60 ceramic resonator circuit .............................................................................................. 1-62 fig. 61 external clock input circuit ............................................................................................ 1-62 fig. 62 system clock generating circuit block diagram (single-chip mode) ........................ 1-63 fig. 63 state transitions of system clock ................................................................................. 1-64 fig. 64 memory maps in various processor modes ................................................................ 1-65 fig. 65 structure of cpu mode register ................................................................................... 1-65 fig. 66 onw function timing ...................................................................................................... 1-66 fig. 67 programming and testing of one time prom version ............................................ 1-67 fig. 68 pin connection of m38869ffahp/gp when operating in parallel input/output mode ... 1-70 fig. 69 read timing ..................................................................................................................... 1-71 fig. 70 timings during reading .................................................................................................. 1-72 fig. 71 input/output timings during programming (verify data is output at the same timing as for read.) ......................................................................................................................... 1-73 fig. 72 input/output timings during erasing (verify data is output at the same timing as for read.) ............................................................................................................................... 1-74 fig. 73 programming/erasing algorithm flow chart ................................................................. 1-76 fig. 74 pin connection of m38869ffahp/gp when operating in serial i/o mode ............ 1-78 fig. 75 timings during reading .................................................................................................. 1-80 fig. 76 timings during programming ......................................................................................... 1-81 fig. 77 timings during program verify ...................................................................................... 1-81 fig. 78 timings at erasing .......................................................................................................... 1-82 fig. 79 timings during erase verify ........................................................................................... 1-82 fig. 80 timings at error checking .............................................................................................. 1-83 fig. 81 flash memory control register bit configuration ......................................................... 1-85 fig. 82 flash command register bit configuration ................................................................... 1-86 fig. 83 cpu mode register bit configuration in cpu rewriting mode .................................. 1-86 fig. 84 flowchart of program/erase operation at cpu reprogramming mode .................... 1-88 fig. 85 a-d conversion equivalent circuit ................................................................................. 1-92 fig. 86 a-d conversion timing chart .......................................................................................... 1-92 chapter 2 application fig. 2.1.1 memory map of registers relevant to i/o port ......................................................... 2-2 fig. 2.1.2 structure of port pi (i = 0 to 8) ................................................................................. 2-3 fig. 2.1.3 structure of port pi direction register (i = 0 to 8) .................................................. 2-3 fig. 2.1.4 structure of port control register 1 ............................................................................ 2-4 fig. 2.1.5 structure of port control register 2 ............................................................................ 2-4 fig. 2.2.1 memory map of registers relevant to interrupt ........................................................ 2-8
vii 3886 group user s manual list of figures fig. 2.2.2 structure of port control register 2 ............................................................................ 2-8 fig. 2.2.3 structure of interrupt source selection register ....................................................... 2-9 fig. 2.2.4 structure of interrupt edge selection register .......................................................... 2-9 fig. 2.2.5 structure of interrupt request register 1 ................................................................. 2-10 fig. 2.2.6 structure of interrupt request register 2 ................................................................. 2-10 fig. 2.2.7 structure of interrupt control register 1 .................................................................. 2-11 fig. 2.2.8 structure of interrupt control register 2 .................................................................. 2-11 fig. 2.2.9 interrupt operation diagram ....................................................................................... 2-13 fig. 2.2.10 changes of stack pointer and program counter upon acceptance of interrupt request .. 2-14 fig. 2.2.11 time up to execution of interrupt processing routine ......................................... 2-15 fig. 2.2.12 timing chart after acceptance of interrupt request ............................................. 2-15 fig. 2.2.13 interrupt control diagram ......................................................................................... 2-16 fig. 2.2.14 example of multiple interrupts ................................................................................ 2-18 fig. 2.2.15 connection example and port p3 block diagram when using key input interrupt .. 2-20 fig. 2.2.16 registers setting relevant to key input interrupt (corresponding to figure 2.2.15) ...2-21 fig. 2.2.17 sequence of switching detection edge ................................................................. 2-22 fig. 2.2.18 sequence of check of interrupt request bit .......................................................... 2-22 fig. 2.2.19 sequence of changing relevant register ............................................................... 2-23 fig. 2.3.1 memory map of registers relevant to timers .......................................................... 2-24 fig. 2.3.2 structure of prescaler 12, prescaler x, prescaler y ............................................ 2-24 fig. 2.3.3 structure of timer 1 .................................................................................................. 2-25 fig. 2.3.4 structure of timer 2, timer x, timer y ................................................................. 2-25 fig. 2.3.5 structure of timer xy mode register ...................................................................... 2-26 fig. 2.3.6 structure of port control register 2 .......................................................................... 2-27 fig. 2.3.7 structure of interrupt request register 1 ................................................................. 2-28 fig. 2.3.8 structure of interrupt request register 2 ................................................................. 2-28 fig. 2.3.9 structure of interrupt control register 1 .................................................................. 2-29 fig. 2.3.10 structure of interrupt control register 2 ................................................................ 2-29 fig. 2.3.11 timers connection and setting of division ratios ................................................. 2-31 fig. 2.3.12 relevant registers setting ....................................................................................... 2-31 fig. 2.3.13 control procedure ..................................................................................................... 2-32 fig. 2.3.14 peripheral circuit example ....................................................................................... 2-33 fig. 2.3.15 timers connection and setting of division ratios ................................................. 2-33 fig. 2.3.16 relevant registers setting ....................................................................................... 2-34 fig. 2.3.17 control procedure ..................................................................................................... 2-34 fig. 2.3.18 judgment method of valid/invalid of input pulses ............................................... 2-35 fig. 2.3.19 relevant registers setting ....................................................................................... 2-36 fig. 2.3.20 control procedure ..................................................................................................... 2-37 fig. 2.3.21 timers connection and setting of division ratios ................................................. 2-38 fig. 2.3.22 relevant registers setting ....................................................................................... 2-39 fig. 2.3.23 control procedure ..................................................................................................... 2-40 fig. 2.4.1 memory map of registers relevant to serial i/o .................................................... 2-42 fig. 2.4.2 structure of transmit/receive buffer register ........................................................ 2-43 fig. 2.4.3 structure of serial i/o status register ..................................................................... 2-43 fig. 2.4.4 structure of serial i/o1 control register .................................................................. 2-44 fig. 2.4.5 structure of uart control register .......................................................................... 2-44 fig. 2.4.6 structure of baud rate generator ............................................................................. 2-45 fig. 2.4.7 structure of serial i/o2 control register .................................................................. 2-45 fig. 2.4.8 structure of serial i/o2 register ............................................................................... 2-46 fig. 2.4.9 structure of interrupt source selection register ..................................................... 2-46 fig. 2.4.10 structure of interrupt edge selection register ...................................................... 2-47 fig. 2.4.11 structure of interrupt request register 1 ............................................................... 2-48
viii 3886 group user s manual list of figures fig. 2.4.12 structure of interrupt request register 2 ............................................................... 2-48 fig. 2.4.13 structure of interrupt control register 1 ................................................................ 2-49 fig. 2.4.14 structure of interrupt control register 2 ................................................................ 2-49 fig. 2.4.15 serial i/o connection examples (1) ....................................................................... 2-50 fig. 2.4.16 serial i/o connection examples (2) ....................................................................... 2-51 fig. 2.4.17 serial i/o transfer data format ............................................................................... 2-52 fig. 2.4.18 connection diagram ................................................................................................. 2-53 fig. 2.4.19 timing chart .............................................................................................................. 2-53 fig. 2.4.20 registers setting relevant to transmitting side ..................................................... 2-54 fig. 2.4.21 registers setting relevant to receiving side ......................................................... 2-55 fig. 2.4.22 control procedure of transmitting side .................................................................. 2-56 fig. 2.4.23 control procedure of receiving side ...................................................................... 2-57 fig. 2.4.24 connection diagram ................................................................................................. 2-58 fig. 2.4.25 timing chart .............................................................................................................. 2-58 fig. 2.4.26 registers setting relevant to serial i/o1 .............................................................. 2-59 fig. 2.4.27 setting of serial i/o1 transmission data ............................................................... 2-59 fig. 2.4.28 control procedure of serial i/o1 ............................................................................ 2-60 fig. 2.4.29 registers setting relevant to serial i/o2 .............................................................. 2-61 fig. 2.4.30 setting of serial i/o2 transmission data ............................................................... 2-61 fig. 2.4.31 control procedure of serial i/o2 ............................................................................ 2-62 fig. 2.4.32 connection diagram ................................................................................................. 2-63 fig. 2.4.33 timing chart .............................................................................................................. 2-64 fig. 2.4.34 relevant registers setting ....................................................................................... 2-64 fig. 2.4.35 control procedure of master unit ........................................................................... 2-65 fig. 2.4.36 control procedure of slave unit ............................................................................. 2-66 fig. 2.4.37 connection diagram (communication using uart) ............................................ 2-67 fig. 2.4.38 timing chart (using uart) ..................................................................................... 2-67 fig. 2.4.39 registers setting relevant to transmitting side ..................................................... 2-69 fig. 2.4.40 registers setting relevant to receiving side ......................................................... 2-70 fig. 2.4.41 control procedure of transmitting side .................................................................. 2-71 fig. 2.4.42 control procedure of receiving side ...................................................................... 2-72 fig. 2.4.43 sequence of setting serial i/o1 control register again ....................................... 2-74 fig. 2.5.1 memory map of registers relevant to i 2 c-bus interface ...................................... 2-76 fig. 2.5.2 structure of i 2 c data shift register ........................................................................... 2-76 fig. 2.5.3 structure of i 2 c address register ............................................................................. 2-77 fig. 2.5.4 structure of i 2 c status register ................................................................................. 2-77 fig. 2.5.5 structure of i 2 c control register ............................................................................... 2-78 fig. 2.5.6 structure of i 2 c clock control register ..................................................................... 2-79 fig. 2.5.7 structure of i 2 c start/stop condition control register ..................................... 2-80 fig. 2.5.8 structure of interrupt source selection register ..................................................... 2-80 fig. 2.5.9 structure of interrupt request register 1 ................................................................. 2-81 fig. 2.5.10 structure of interrupt request register 2 ............................................................... 2-81 fig. 2.5.11 structure of interrupt control register 1 ................................................................ 2-82 fig. 2.5.12 structure of interrupt control register 2 ................................................................ 2-82 fig. 2.5.13 i 2 c-bus connection structure ................................................................................. 2-83 fig. 2.5.14 i 2 c-bus communication format example .............................................................. 2-84 fig. 2.5.15 restart condition of master reception .............................................................. 2-85 fig. 2.5.16 scl waveforms when synchronizing clocks ......................................................... 2-86 fig. 2.5.17 initial setting example .............................................................................................. 2-88 fig. 2.5.18 read word protocol communication as i 2 c-bus master device ....................... 2-89 fig. 2.5.19 generating of start condition and transmission process of slave address + write bit.. 2-90 fig. 2.5.20 transmission process of command ....................................................................... 2-91
ix 3886 group user s manual list of figures fig. 2.5.21 transmission process of restart condition and slave address + read bit . 2-92 fig. 2.5.22 reception process of lower data ........................................................................... 2-93 fig. 2.5.23 reception process of upper data .......................................................................... 2-94 fig. 2.5.24 generating of stop condition ............................................................................... 2-95 fig. 2.5.25 communication example as slave device ............................................................. 2-96 fig. 2.5.26 reception process of start condition and slave address .............................. 2-97 fig. 2.5.27 reception process of command ............................................................................. 2-98 fig. 2.5.28 reception process of restart condition and slave address ......................... 2-99 fig. 2.5.29 transmission process of lower data .................................................................... 2-100 fig. 2.5.30 transmission process of upper data ................................................................... 2-101 fig. 2.5.31 reception of stop condition ............................................................................... 2-102 fig. 2.6.1 memory map of registers relevant to pwm ......................................................... 2-106 fig. 2.6.2 structure of port control register 1 ........................................................................ 2-107 fig. 2.6.3 structure of pwm0h register ................................................................................. 2-108 fig. 2.6.4 structure of pwm0l register .................................................................................. 2-108 fig. 2.6.5 structure of pwm1h register ................................................................................. 2-109 fig. 2.6.6 structure of pwm1l register .................................................................................. 2-109 fig. 2.6.7 structure of ad/da control register ....................................................................... 2-110 fig. 2.6.8 connection diagram ................................................................................................. 2-111 fig. 2.6.9 relevant registers setting ....................................................................................... 2-112 fig. 2.6.10 control procedure ................................................................................................... 2-113 fig. 2.6.11 pwm 0 output ........................................................................................................... 2-113 fig. 2.7.1 memory map of registers relevant to a-d converter .......................................... 2-114 fig. 2.7.2 structure of ad/da control register ....................................................................... 2-114 fig. 2.7.3 structure of a-d conversion register 1 ................................................................. 2-115 fig. 2.7.4 structure of a-d conversion register 2 ................................................................. 2-115 fig. 2.7.5 structure of interrupt source selection register ................................................... 2-116 fig. 2.7.6 structure of interrupt request register 2 ............................................................... 2-117 fig. 2.7.7 structure of interrupt control register 2 ................................................................ 2-117 fig. 2.7.8 connection diagram ................................................................................................. 2-118 fig. 2.7.9 relevant registers setting ....................................................................................... 2-118 fig. 2.7.10 control procedure for 8-bit read .......................................................................... 2-119 fig. 2.7.11 control procedure for 10-bit read ........................................................................ 2-119 fig. 2.8.1 memory map of registers relevant to d-a converter .......................................... 2-121 fig. 2.8.2 structure of port p5 direction register .................................................................. 2-122 fig. 2.8.3 structure of ad/da control register ....................................................................... 2-122 fig. 2.8.4 structure of d-ai converter register ...................................................................... 2-123 fig. 2.8.5 peripheral circuit example ....................................................................................... 2-124 fig. 2.8.6 speaker output example ......................................................................................... 2-124 fig. 2.8.7 relevant registers setting ....................................................................................... 2-125 fig. 2.8.8 control procedure ..................................................................................................... 2-126 fig. 2.9.1 memory map of registers relevant to bus interface ............................................ 2-128 fig. 2.9.2 structure of data bus buffer register i .................................................................. 2-129 fig. 2.9.3 structure of data bus buffer status register i ...................................................... 2-129 fig. 2.9.4 structure of data bus buffer control register ....................................................... 2-130 fig. 2.9.5 structure of interrupt source selection register ................................................... 2-130 fig. 2.9.6 structure of interrupt request register 1 ............................................................... 2-131 fig. 2.9.7 structure of interrupt control register 1 ................................................................ 2-131 fig. 2.9.8 structure of port control register 2 ........................................................................ 2-132 fig. 2.9.9 bus interface block diagram ................................................................................... 2-133 fig. 2.9.10 relevant registers setting ..................................................................................... 2-135 fig. 2.9.11 control procedure using interrupt ........................................................................ 2-136
x 3886 group user s manual list of figures fig. 2.10.1 memory map of registers relevant to watchdog timer ...................................... 2-137 fig. 2.10.2 structure of watchdog timer control register ..................................................... 2-137 fig. 2.10.3 structure of cpu mode register .......................................................................... 2-138 fig. 2.10.4 watchdog timer connection and division ratio setting ...................................... 2-139 fig. 2.10.5 relevant registers setting ..................................................................................... 2-140 fig. 2.10.6 control procedure ................................................................................................... 2-140 fig. 2.11.1 example of poweron reset circuit ........................................................................ 2-141 fig. 2.11.2 ram backup system .............................................................................................. 2-141 fig. 2.12.1 structure of cpu mode register .......................................................................... 2-143 fig. 2.12.2 connection diagram ............................................................................................... 2-144 fig. 2.12.3 status transition diagram during power failure .................................................. 2-144 fig. 2.12.4 setting of relevant registers ................................................................................. 2-145 fig. 2.12.5 control procedure ................................................................................................... 2-146 fig. 2.13.1 oscillation stabilizing time at restoration by reset input .................................. 2-148 fig. 2.13.2 execution sequence example at restoration by occurrence of int 0 interrupt request .. 2-150 fig. 2.13.3 reset input time ..................................................................................................... 2-152 fig. 2.14.1 memory map of registers relevant to processor mode ..................................... 2-154 fig. 2.14.2 structure of cpu mode register .......................................................................... 2-154 fig. 2.14.3 expansion example of 32-kbytes rom and ram ............................................ 2-155 fig. 2.14.4 read cycle (oe access, sram) .......................................................................... 2-156 fig. 2.14.5 read cycle (oe access, eprom) ....................................................................... 2-156 fig. 2.14.6 write cycle (w control, sram) ............................................................................ 2-157 fig. 2.14.7 usage example of onw function ........................................................................ 2-158 fig. 2.14.8 expansion example of 32-kbytes rom and ram at f(x in ) = 8 mhz or more ... 2-159 fig. 2.14.9 read cycle (oe access, sram) .......................................................................... 2-160 fig. 2.14.10 read cycle (oe access, eprom) ..................................................................... 2-160 fig. 2.14.11 write cycle (w control, sram) .......................................................................... 2-161 fig. 2.15.1 memory map of flash memory version for 3886 group ................................... 2-162 fig. 2.15.2 memory map of registers relevant to flash memory ......................................... 2-163 fig. 2.15.3 structure of flash memory control register ........................................................ 2-163 fig. 2.15.4 structure of flash command register .................................................................. 2-164 fig. 2.15.5 reprogramming example of built-in flash memory in serial i/o mode ........... 2-167 fig. 2.15.6 connection example in serial i/o mode (1) ....................................................... 2-168 fig. 2.15.7 connection example in serial i/o mode (2) ....................................................... 2-168 fig. 2.15.8 connection example in serial i/o mode (3) ....................................................... 2-169 fig. 2.15.9 example of reprogramming system for built-in flash memory in cpu reprogramming mode ... 2-170 fig. 2.15.10 cpu reprogramming control program example (1) ......................................... 2-171 fig. 2.15.11 cpu reprogramming control program example (2) ......................................... 2-172 fig. 2.15.12 cpu reprogramming control program example (3) ......................................... 2-173 fig. 2.15.13 cpu reprogramming control program example (4) ......................................... 2-174 fig. 2.15.14 v pp control circuit example (1) ........................................................................... 2-175 fig. 2.15.15 v pp control circuit example (2) ........................................................................... 2-175 chapter 3 appendix fig. 3.1.1 circuit for measuring output switching characteristics (1) ................................... 3-12 fig. 3.1.2 circuit for measuring output switching characteristics (2) ................................... 3-12 fig. 3.1.3 timing diagram (1) (in single-chip mode) ............................................................... 3-13 fig. 3.1.4 timing diagram (2) (in memory expansion mode and microprocessor mode) .. 3-14 fig. 3.1.5 timing diagram (3) (in memory expansion mode and microprocessor mode) .. 3-15 fig. 3.1.6 timing diagram (4) (system bus interface) ............................................................ 3-16
xi 3886 group user s manual list of figures fig. 3.1.7 timing diagram of multi-master i 2 c-bus ................................................................ 3-17 fig. 3.2.1 power source current characteristic examples (in high-speed mode, a-d conversion and comparator operating) ........................................................................................ 3-18 fig. 3.2.2 power source current characteristic examples (in high-speed mode) ................ 3-18 fig. 3.2.3 power source current characteristic examples (in high-speed mode, wait execution) . 3-19 fig. 3.2.4 power source current characteristic examples (in middle-speed mode) ............ 3-19 fig. 3.2.5 power source current characteristic examples (in middle-speed mode, wait execution) . 3-20 fig. 3.2.6 power source current characteristic examples (in low-speed mode) ................. 3-20 fig. 3.2.7 power source current characteristic examples (at reset) ..................................... 3-21 fig. 3.2.8 standard characteristic examples of cmos output port at p-channel drive (ta=25 c) .. 3-22 fig. 3.2.9 standard characteristic examples of cmos output port at p-channel drive (ta=90 c) ... 3-22 fig. 3.2.10 standard characteristic examples of cmos output port at n-channel drive (ta=25 c) ... 3-23 fig. 3.2.11 standard characteristic examples of cmos output port at n-channel drive (ta=90 c) .. 3-23 fig. 3.2.12 standard characteristic examples of cmos large current output port at n-channel drive (ta=25 c) ...................................................................................................... 3-24 fig. 3.2.13 standard characteristic examples of cmos large current output port at n-channel drive (ta=90 c) ...................................................................................................... 3-24 fig. 3.2.14 standard characteristic examples of cmos input port at pull-up (ta=25 c) .. 3-25 fig. 3.2.15 standard characteristic examples of cmos input port at pull-up (ta=90 c) .. 3-25 fig. 3.2.16 a-d conversion standard characteristics ............................................................... 3-26 fig. 3.2.17 d-a conversion standard characteristics ............................................................... 3-27 fig. 3.3.1 sequence of switch the detection edge .................................................................. 3-30 fig. 3.3.2 sequence of check of interrupt request bit ............................................................ 3-30 fig. 3.3.3 sequence of changing relevant register ................................................................. 3-31 fig. 3.3.4 sequence of setting serial i/o1 control register again ......................................... 3-33 fig. 3.3.5 pwm 0 output ............................................................................................................... 3-37 fig. 3.3.6 ceramic resonator circuit .......................................................................................... 3-39 fig. 3.3.7 initialization of processor status register ................................................................ 3-40 fig. 3.3.8 sequence of plp instruction execution .................................................................. 3-40 fig. 3.3.9 stack memory contents after php instruction execution ..................................... 3-40 fig. 3.3.10 interrupt routine .................................................................................................. ...... 3-41 fig. 3.3.11 status flag at decimal calculations ........................................................................ 3-41 fig. 3.3.12 programming and testing of one time prom version ...................................... 3-42 fig. 3.4.1 wiring for the reset pin ......................................................................................... 3-44 fig. 3.4.2 wiring for clock i/o pins ........................................................................................... 3-44 fig. 3.4.3 wiring for cnvss pin ................................................................................................. 3-45 fig. 3.4.4 wiring for the v pp pin of the one time prom version and the eprom version ... 3-45 fig. 3.4.5 bypass capacitor across the vss line and the vcc line ....................................... 3-46 fig. 3.4.6 analog signal line and a resistor and a capacitor ................................................ 3-46 fig. 3.4.7 wiring for a large current signal line ...................................................................... 3-47 fig. 3.4.8 wiring of reset pin ................................................................................................. 3-47 fig. 3.4.9 vss pattern on the underside of an oscillator ....................................................... 3-48 fig. 3.4.10 setup for i/o ports ................................................................................................... 3-48 fig. 3.4.11 watchdog timer by software ................................................................................... 3-49 fig. 3.5.1 structure of port pi .................................................................................................... 3-50 fig. 3.5.2 structure of port pi direction register ..................................................................... 3-50 fig. 3.5.3 structure of i 2 c data shift register ........................................................................... 3-51 fig. 3.5.4 structure of i 2 c address register ............................................................................. 3-51 fig. 3.5.5 structure of i 2 c status register ................................................................................. 3-52 fig. 3.5.6 structure of i 2 c control register ............................................................................... 3-53 fig. 3.5.7 structure of i 2 c clock control register ..................................................................... 3-54 fig. 3.5.8 structure of i 2 c start/stop condition control register ..................................... 3-55
xii 3886 group user s manual list of figures fig. 3.5.9 structure of transmit/receive buffer register ........................................................ 3-55 fig. 3.5.10 structure of serial i/o1 status register ................................................................. 3-56 fig. 3.5.11 structure of serial i/o1 control register ................................................................ 3-56 fig. 3.5.12 structure of uart control register ........................................................................ 3-57 fig. 3.5.13 structure of baud rate generator ........................................................................... 3-57 fig. 3.5.14 structure of serial i/o2 control register ................................................................ 3-58 fig. 3.5.15 structure of watchdog timer control register ....................................................... 3-58 fig. 3.5.16 structure of serial i/o2 register ............................................................................. 3-59 fig. 3.5.17 structure of prescaler 12, prescaler x, prescaler y .......................................... 3-59 fig. 3.5.18 structure of timer 1 ................................................................................................ 3-60 fig. 3.5.19 structure of timer 2, timer x, timer y ............................................................... 3-60 fig. 3.5.20 structure of timer xy mode register .................................................................... 3-61 fig. 3.5.21 structure of data bus buffer register .................................................................... 3-62 fig. 3.5.22 structure of data bus buffer status register ........................................................ 3-62 fig. 3.5.23 structure of data bus buffer control register ....................................................... 3-63 fig. 3.5.24 structure of comparator data register .................................................................. 3-63 fig. 3.5.25 structure of port control register 1 ....................................................................... 3-64 fig. 3.5.26 structure of port control register 2 ....................................................................... 3-64 fig. 3.5.27 structure of pwm0h register ................................................................................. 3-65 fig. 3.5.28 structure of pwm0l register .................................................................................. 3-65 fig. 3.5.29 structure of pwm1h register ................................................................................. 3-66 fig. 3.5.30 structure of pwm1l register .................................................................................. 3-66 fig. 3.5.31 structure of ad/da control register ....................................................................... 3-67 fig. 3.5.32 structure of ad conversion register 1 .................................................................. 3-67 fig. 3.5.33 structure of d-ai conversion register .................................................................... 3-68 fig. 3.5.34 structure of a-d conversion register 2 ................................................................. 3-68 fig. 3.5.35 structure of interrupt source selection register ................................................... 3-69 fig. 3.5.36 structure of interrupt edge selection register ...................................................... 3-69 fig. 3.5.37 structure of cpu mode register ............................................................................ 3-70 fig. 3.5.38 structure of interrupt request register 1 ............................................................... 3-71 fig. 3.5.39 structure of interrupt request register 2 ............................................................... 3-71 fig. 3.5.40 structure of interrupt control register 1 ................................................................ 3-72 fig. 3.5.41 structure of interrupt control register 2 ................................................................ 3-72 fig. 3.5.42 structure of flash memory control register .......................................................... 3-73 fig. 3.5.43 structure of flash command register .................................................................... 3-74 fig. 3.10.1 m38867m8a-xxxhp, m38867e8ahp pin configuration ..................................... 3-89 fig. 3.10.2 m38867e8afs pin configuration ............................................................................ 3-89 fig. 3.10.3 m38869mfa-xxxgp/hp, m38869ffagp/hp pin configuration ........................ 3-90
xiii 3886 group user s manual list of tables list of tables chapter 1 hardware table 1 pin description (1) ........................................................................................................... 1-6 table 2 pin description (2) ........................................................................................................... 1-7 table 3 support products ............................................................................................................. 1-9 table 4 push and pop instructions of accumulator or processor status register ............... 1-11 table 5 set and clear instructions of each bit of processor status register ....................... 1-12 table 6 i/o port function (1) ...................................................................................................... 1-16 table 7 i/o port function (2) ...................................................................................................... 1-17 table 8 interrupt vector addresses and priority ...................................................................... 1-24 table 9 relationship between low-order 6 bits of data and period set by the add bit ... 1-37 table 10 function description of control i/o pins at bus interface function selected ....... 1-43 table 11 multi-master i 2 c-bus interface functions ................................................................. 1-44 table 12 set values of i 2 c clock control register and s cl frequency .................................. 1-46 table 13 start condition generating timing table ................................................................ 1-50 table 14 stop condition generating timing table .................................................................. 1-50 table 15 start condition/stop condition detecting conditions .......................................... 1-50 table 16 recommended set value to start/stop condition set bits (ssc4-ssc0) for each oscillation frequency ................................................................................................... 1-52 table 17 port functions in memory expansion mode and microprocessor mode ............... 1-65 table 18 programming adapter .................................................................................................. 1-67 table 19 prom programmer setup ........................................................................................... 1-67 table 20 pin assignments of m38869ffahp/gp when operating in the parallel input/output mode ............................................................................................................................. 1- 68 table 21 assignment states of control input and each state ................................................ 1-68 table 22 pin description (flash memory parallel i/o mode) .................................................. 1-69 table 23 software command (parallel input/output mode) .................................................... 1-71 table 24 dc electrical characteristics ....................................................................................... 1-77 table 25 read-only mode ........................................................................................................... 1-77 table 26 read/write mode ......................................................................................................... 1-77 table 27 pin description (flash memory serial i/o mode) ..................................................... 1-79 table 28 software command (serial i/o mode) ....................................................................... 1-80 table 29 ac electrical characteristics ....................................................................................... 1-84 table 30 relative formula for a reference voltage v ref of a-d converter and v ref ..................... 1-91 table 31 change of a-d conversion register during a-d conversion .................................. 1-91 chapter 2 application table 2.1.1 handling of unused pins (in single-chip mode) .................................................... 2-5 table 2.1.2 handling of unused pins (in memory expansion mode, microprocessor mode) ...2-5 table 2.2.1 interrupt sources, vector addresses and priority of 3886 group ...................... 2-12 table 2.2.2 list of interrupt bits according to interrupt source ............................................. 2-17 table 2.3.1 cntr 0 /cntr 1 active edge selection bit function ............................................... 2-26 table 2.4.1 setting examples of baud rate generator values and transfer bit rate values ... 2-68 table 2.5.1 set value of i 2 c clock control register and scl frequency .............................. 2-79 table 2.9.1 bus control signals and data bus status ........................................................... 2-134 table 2.13.1 state in stop mode ............................................................................................. 2-147 table 2.13.2 state in wait mode .............................................................................................. 2-151 table 2.15.1 setting of eprom programmers when parallel programming ...................... 2-164
xiv 3886 group user s manual list of tables table 2.15.2 connection example to programmer when serial programming ................... 2-165 chapter 3 appendix table 3.1.1 absolute maximum ratings ....................................................................................... 3-2 table 3.1.2 recommended operating conditions (1) ................................................................ 3-3 table 3.1.3 recommended operating conditions (2) ................................................................ 3-4 table 3.1.4 recommended operating conditions (3) ................................................................ 3-4 table 3.1.5 electrical characteristics (1) ..................................................................................... 3-5 table 3.1.6 electrical characteristics (2) ..................................................................................... 3-6 table 3.1.7 a-d converter characteristics (1) ............................................................................ 3-7 table 3.1.8 a-d converter characteristics (2) ............................................................................ 3-7 table 3.1.9 d-a converter characteristics .................................................................................. 3-7 table 3.1.10 comparator characteristics .................................................................................... 3-7 table 3.1.11 timing requirements (1) ......................................................................................... 3-8 table 3.1.12 timing requirements (2) ......................................................................................... 3-9 table 3.1.13 timing requirements for system bus interface (1) ........................................... 3-10 table 3.1.14 timing requirements for system bus interface (2) ........................................... 3-10 table 3.1.15 switching characteristics (1) ................................................................................ 3-11 table 3.1.16 switching characteristics (2) ................................................................................ 3-11 table 3.1.17 switching characteristics for system bus interface (1) .................................... 3-11 table 3.1.18 switching characteristics for system bus interface (2) .................................... 3-11 table 3.1.19 timing requirements in memory expansion mode and microprocessor mode . 3-12 table 3.1.20 switching characteristics in memory expansion mode and microprocessor mode .. 3-12 table 3.1.21 multi-master i 2 c-bus bus line characteristics .................................................. 3-17 table 3.3.1 programming adapters ........................................................................................... 3-43 table 3.3.2 prom programmer address setting ..................................................................... 3-43 table 3.5.1 set value of i 2 c clock control register and scl frequency .............................. 3-54 table 3.5.2 cntr 0 /cntr 1 active edge selection bit function ............................................... 3-61
chapter 1 hardware description features application pin configuration functional block pin description part numbering group expansion functional description notes on programming notes on use data required for mask orders data required for one time prom programming orders functional description supplement
hardware 1-2 3886 group user? manual description the 3886 group is the 8-bit microcomputer based on the 740 fam- ily core technology. the 3886 group is designed for controlling systems that require analog signal processing and include two serial i/o functions, a-d converters, d-a converters, system data bus interface function, watchdog timer, and comparator circuit. the multi-master i 2 c-bus interface can be added by option. features basic machine-language instructions ...................................... 71 minimum instruction execution time .................................. 0.4 s (at 10 mhz oscillation frequency) memory size rom ................................................................. 32k to 60k bytes ram ............................................................... 1024 to 2048 bytes programmable input/output ports ............................................ 72 software pull-up resistors ................................................. built-in interrupts ................................................. 21 sources, 16 vectors (included key input interrupt) timers ............................................................................. 8-bit ? 4 serial i/o1 .................... 8-bit ? 1(uart or clock-synchronized) serial i/o2 ................................... 8-bit ? 1(clock-synchronized) pwm output circuit ....................................................... 14-bit ? 2 bus interface .................................................................... 2 bytes i 2 c-bus interface (option) ........................................... 1 channel a-d converter ............................................... 10-bit ? 8 channels d-a converter ................................................. 8-bit ? 2 channels comparator circuit ...................................................... 8 channels watchdog timer ............................................................ 16-bit ? 1 clock generating circuit ..................................... built-in 2 circuits (connect to external ceramic resonator or quartz-crystal oscillator) power source voltage in high-speed mode .................................................. 4.0 to 5.5 v (at 10 mhz oscillation frequency) in middle-speed mode ........................................... 2.7 to 5.5 v(*) (at 10 mhz oscillation frequency) in low-speed mode ............................................... 2.7 to 5.5 v (*) (at 32 khz oscillation frequency) (*: 4.0 to 5.5 v for flash memory version) power dissipation in high-speed mode .......................................................... 40 mw (at 10 mhz oscillation frequency, at 5 v power source voltage) in low-speed mode ............................................................ 60 w (at 32 khz oscillation frequency, at 3 v power source voltage) memory expansion possible (only for m38867m8a/e8a) operating temperature range .................................... ?0 to 85? supply voltage (at programming/erasing) ...... v cc = 5 v ?10 % program/erase voltage ............................... v pp = 11.7 to 12.6 v programming method ...................... programming in unit of byte erasing method batch erasing ........................................ parallel/serial i/o mode block erasing .................................... cpu reprogramming mode program/erase control by software command number of times for programming/erasing ............................ 100 operating temperature range (at programming/erasing) ..................................................................... normal temperature notes 1. the flash memory version cannot be used for application em- bedded in the mcu card. 2. power source voltage vcc of the flash memory version is 4.0 to 5.5 v. application household product, consumer electronics, communications, note book pc, etc. description/features
1-3 3886 group user? manual hardware package type : 80d0 pin configuration (top view) note: the pin number and the position of the function pin may change by the kind of package. fig. 2 m38867e8afs pin configuration package type : 80p6q-a pin configuration (top view) note: the pin number and the position of the function pin may change by the kind of package. fig. 1 m38867m8a-xxxhp, m38867e8ahp pin configuration : prom version pin configuration : prom version 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p 6 2 / a n 2 p 6 1 / a n 1 p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 a v s s p 6 7 / a n 7 v r e f v c c p 8 0 / d q 0 p 8 1 / d q 1 p 8 2 / d q 2 p 8 3 / d q 3 p 8 4 / d q 4 p 8 5 / d q 5 p 8 6 / d q 6 p8 7 /dq 7 p 4 2 / i n t 0 / o b f 0 0 c n v s s x in x out v ss r e s e t p4 0 /x cou t p4 1 /x cin p1 6 /ad 14 p1 7 /ad 15 p2 6 /db 6 p2 5 /db 5 p2 4 /db 4 p2 3 /db 3 p2 2 /db 2 p2 1 /db 1 p 2 0 / d b 0 p 3 4 /
hardware 1-4 3886 group user s manual fig. 3 m38869mfa-xxxgp/hp, m38869ffagp/hp pin configuration note: the pin number and the position of the function pin may change by the kind of package. : flash memory version package type : 80p6s-a/80p6q-a pin configuration (top view) pin configuration 2 1 2 2 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 3 1 3 2 3 3 3 4 3 5 3 6 3 7 3 8 3 9 4 0 4 1 4 2 4 3 4 4 4 5 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 5 5 5 6 5 7 5 8 5 9 6 0 6 1 6 2 6 3 6 4 6 5 6 6 6 7 6 8 6 9 7 0 7 1 7 2 7 3 7 4 7 5 7 6 7 7 7 8 7 9 8 0 p 3 0 / p w m 0 0 p 3 1 / p w m 1 0 p 6 2 / a n 2 p 6 1 / a n 1 p 4 4 / r x d p 4 3 / i n t 1 / o b f 0 1 p 6 3 / a n 3 p 6 4 / a n 4 p 6 5 / a n 5 p 6 6 / a n 6 a v s s p 6 7 / a n 7 v r e f v c c p 8 0 / d q 0 p 8 1 / d q 1 p 8 2 / d q 2 p 8 3 / d q 3 p 8 4 / d q 4 p 8 5 / d q 5 p 8 6 / d q 6 p 8 7 / d q 7 p 4 2 / i n t 0 / o b f 0 0 c n v s s x i n x o u t v s s r e s e t p 4 0 / x c o u t p 4 1 / x c i n p 1 6 p 1 7 p 2 6 p 2 5 p 2 4 p 2 3 p 2 2 p 2 1 p 2 0 p 3 4 p 3 5 p 0 0 / p 3 r e f p 0 4 p 0 5 p 0 6 p 0 7 p 1 1 p 1 2 p 1 3 p 1 4 p 1 5 p 1 0 p 0 1 p 0 2 p 3 2 p 3 3 p 3 6 p 3 7 p 0 3 p 2 7 p 6 0 / a n 0 p 7 7 / s c l p 7 6 / s d a p 7 5 / i n t 4 1 p 7 4 / i n t 3 1 p 7 2 / s c l k 2 p 7 1 / s o u t 2 p 7 0 / s i n 2 p 5 7 / d a 2 / p w m 1 1 p 5 0 / a 0 p 4 5 / t x d p 7 3 / s r d y 2 / i n t 2 1 p 5 5 / c n t r 1 p 5 4 / c n t r 0 p 5 6 / d a 1 / p w m 0 1 p 4 7 / s r d y 1 / s 1 p 5 2 / i n t 3 0 / r p 5 3 / i n t 4 0 / w p 5 1 / i n t 2 0 / s 0 p 4 6 / s c l k 1 / o b f 1 0 1 2 3 4 7 8 9 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 5 6 m 3 8 8 6 9 m f a - x x x g p / h p m 3 8 8 6 9 f f a g p / h p v p p
1-5 3886 group user s manual hardware functional block diagram (package : 80p6q-a, 80p6s-a) fig. 4 functional block diagram functional block i n t 0 , c n t r 0 c n t r 1 v r e f a v s s r a m r o m c p u a x y s p c h p c l p s v s s 3 0 r e s e t 2 5 v c c 7 1 2 4 c n v s s p 5 ( 8 ) p 7 ( 8 ) 2 4 6 8 3 5 7 9 p 8 ( 8 ) p 6 ( 8 ) 7 4 7 6 7 8 8 0 7 5 7 7 7 9 1 7 2 7 3 x i n 2 8 2 9 s i / o 1 ( 8 ) s i / o 2 ( 8 ) d - a c o n v e r t e r 2 ( 8 ) r e s e t i n p u t c l o c k g e n e r a t i n g c i r c u i t m a i n - c l o c k i n p u t m a i n - c l o c k o u t p u t a - d c o n v e r t e r ( 1 0 ) t i m e r y ( 8 ) t i m e r x ( 8 ) p r e s c a l e r 1 2 ( 8 ) p r e s c a l e r x ( 8 ) p r e s c a l e r y ( 8 ) t i m e r 1 ( 8 ) t i m e r 2 ( 8 ) i / o p o r t p 5 i / o p o r t p 7 i / o p o r t p 8 i / o p o r t p 6 s u b - c l o c k i n p u t x o u t x c i n x c o u t s u b - c l o c k o u t p u t w a t c h d o g t i m e r r e s e t p 0 ( 8 ) p 1 ( 8 ) p 2 ( 8 ) p 3 ( 8 ) i / o p o r t p 0 i / o p o r t p 1 i / o p o r t p 2 i / o p o r t p 3 p 3 r e f k e y - o n w a k e - u p x c i n x c o u t p 4 ( 8 ) i / o p o r t p 4 c o m p a r a t o r i n t 1 p w m 0 ( 1 4 ) p w m 1 ( 1 4 ) p w m 0 0 , p w m 0 1 p w m 1 0 , p w m 1 1 d q 0 t o d q 7 b u s i n t e r f a c e i c 2 s c l s d a i n t 4 1 i n t 2 1 , i n t 3 1 , i n t 4 0 i n t 2 0 , i n t 3 0 , 6 3 6 5 6 7 6 9 6 4 6 6 6 8 7 0 d - a c o n v e r t e r 1 ( 8 ) 1 0 1 2 1 4 1 6 1 1 1 3 1 5 1 7 1 8 2 0 2 2 2 6 1 9 2 1 2 3 2 7 5 5 5 7 5 9 6 1 5 6 5 8 6 0 6 2 3 1 3 3 3 5 3 7 3 2 3 4 3 6 3 8 3 9 4 1 4 3 4 5 4 0 4 2 4 4 4 6 4 7 4 8 4 9 5 0 5 1 5 2 5 3 5 4 functional block
hardware 1-6 3886 group user s manual v cc , v ss pin description functions name pin apply voltage of 2.7 v 5.5 v to vcc, and 0 v to vss. in the flash memory version, apply voltage of 4.0 v 5.5 v to vcc, and 0 v to vss. this pin controls the operation mode of the chip. normally connected to v ss . if this pin is connected to vcc, the internal rom is inhibited and an external memory is accessed. in the flash memory version, connected to v ss. in the eprom version or the flash memory version, this pin functions as the v pp power source input pin. reference voltage input pin for a-d and d-a converters. analog power source input pin for a-d and d-a converters. connect to v ss . reset input pin for active l . input and output pins for the clock generating circuit. connect a ceramic resonator or quartz-crystal oscillator between the x in and x out pins to set the oscillation frequency. when an external clock is used, connect the clock source to the x in pin and leave the x out pin open. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the address bus. cmos compatible input level. cmos 3-state output structure or n-channel open-drain output structure. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the address bus. cmos compatible input level. cmos 3-state output structure or n-channel open-drain output structure. 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the data bus. cmos compatible input level. cmos 3-state output structure. p2 4 to p2 7 (4 bits) are enabled to output large current for led drive (only in single-chip mode). 8-bit cmos i/o port. i/o direction register allows each pin to be individually programmed as either input or output. when the external memory is used, these pins are used as the control bus. cmos compatible input level. cmos 3-state output structure. these pins function as key-on wake-up and compara- tor input. these pins are enabled to control pull-up. power source table 1 pin description (1) function except a port function comparator reference power source input pin key-on wake-up input pin comparator input pin pwm output pin key-on wake-up input pin comparator input pin reference voltage analog power source clock input clock output i/o port p0 i/o port p1 i/o port p2 v ref av ss p3 0 /pwm 00 p3 1 /pwm 10 cnv ss input cnv ss reset reset input x in x out p0 0 /p3 ref p0 1 p0 7 p1 0 p1 7 p2 0 p2 7 i/o port p3 p3 2 p3 7 pin description
1-7 3886 group user s manual hardware p5 1 /int 20 /s 0 p5 2 /int 30 /r p5 3 /int 40 /w functions name pin p4 0 /x cout p4 1 /x cin i/o port p4 8-bit i/o port with the same function as port p0. p4 0 , p4 1 : cmos input level p4 2 p4 6 : cmos compatible input level or ttl in- put level p4 7 : cmos compatible input level or ttl input level in the bus interface function